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          Renesas-RH850  CPU System - Overview
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<p>Renesas学习笔记<br>CPU System: Overview</p>
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<p>CPU系统由以下模块组成：</p>
<h4 id="CPU0-PE0-CPU1-PE1-CPU2-PE2-CPU3-PE3-："><a href="#CPU0-PE0-CPU1-PE1-CPU2-PE2-CPU3-PE3-：" class="headerlink" title="CPU0 (PE0), CPU1 (PE1), CPU2 (PE2), CPU3 (PE3)："></a>CPU0 (PE0), CPU1 (PE1), CPU2 (PE2), CPU3 (PE3)：</h4><p>每个<code>PE</code>包含一个主CPU，还包括一个检查核，以确保安全。</p>
<h4 id="ICUMHA："><a href="#ICUMHA：" class="headerlink" title="ICUMHA："></a>ICUMHA：</h4><p>ICUMHA （Intelligent Cryptographic Unit&#x2F;Master）是一种硬件安全模块。ICUMHA可以通过Option Byte设置激活。</p>
<h4 id="Local-RAM："><a href="#Local-RAM：" class="headerlink" title="Local RAM："></a>Local RAM：</h4><p>每个PE都有一个高速可访问的本地RAM。</p>
<h4 id="Cluster-RAM："><a href="#Cluster-RAM：" class="headerlink" title="Cluster RAM："></a>Cluster RAM：</h4><p>集群RAM是所有pe共享的大容量片上RAM。该RAM的某些区域起 retention RAM 的作用。</p>
<h4 id="Code-Flash"><a href="#Code-Flash" class="headerlink" title="Code Flash:"></a>Code Flash:</h4><p>包括用于程序存储的大量代码闪存。所有<code>PE</code>和<code>ICUMHA</code>共享代码flash，它们通过本地&#x2F;全局flash总线相互连接。</p>
<h4 id="Emulation-RAM"><a href="#Emulation-RAM" class="headerlink" title="Emulation RAM:"></a>Emulation RAM:</h4><p>这是模拟代码 flash 的 RAM。这些程序可以通过外部工具的控制来替换而无需重写代码 flash。<br>RH850&#x2F;U2A-EVA 和 RH850&#x2F;U2A6 支持</p>
<h4 id="Data-Flash"><a href="#Data-Flash" class="headerlink" title="Data Flash:"></a>Data Flash:</h4><p>这是可由 CPU 重写的闪存。</p>
<h4 id="Instrumentation-RAM："><a href="#Instrumentation-RAM：" class="headerlink" title="Instrumentation RAM："></a>Instrumentation RAM：</h4><p>仪表 RAM 是作为 RH850 第 2 代调试功能并入的数据保存 RAM 区域，用于工具输出。仅在 RH850&#x2F;U2A-EVA 中受支持。</p>
<h4 id="P-Bus-and-H-Bus-and-I-Bus："><a href="#P-Bus-and-H-Bus-and-I-Bus：" class="headerlink" title="P-Bus and H-Bus and I-Bus："></a>P-Bus and H-Bus and I-Bus：</h4><p>外围IP连接在P总线、H总线和I总线上。<br>对于U2A-EVA、U2A16、U2A8：</p>
<ul>
<li>P总线由10个组组成，P总线组0到9。 </li>
<li>H总线由4组组成，H总线组0到3。 </li>
<li>I总线由3组组成，I总线组0到2。</li>
</ul>
<p>对于U2A6： </p>
<ul>
<li>P总线由10组组成，P总线组0到9。</li>
<li>H总线由2组组成，H总线组1和3。</li>
<li>I总线由3组组成，I总线组0到2。</li>
</ul>
<h4 id="INTC1-INTC2"><a href="#INTC1-INTC2" class="headerlink" title="INTC1, INTC2:"></a>INTC1, INTC2:</h4><p>INTC1 是每个 PE 独享的中断控制器。<br>INTC2 是所有 PE 可以共享的公共中断控制器，它可以通过寄存器设置中断请求的目标 PE。</p>
<h4 id="DMA"><a href="#DMA" class="headerlink" title="DMA:"></a>DMA:</h4><p>DMA 包括两个DMA传输模块，sDMAC和DTS。DTS包含用于安全保证的检查逻辑。</p>

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